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a precision, 16 mhz cbfet op amp ad845 connection diagrams features replaces hybrid amplifiers in many applications ac performance: settles to 0.01% in 350 ns 100 v/ s slew rate 12.8 mhz min unity gain bandwidth 1.75 mhz full power bandwidth at 20 v p-p dc performance: 0.25 mv max input offset voltage 5 v/ c max offset voltage drift 0.5 na input bias current 250 v/mv min open-loop gain 4 v p-p max voltage noise, 0.1 hz to 10 hz 94 db min cmrr available in plastic mini-dip, hermetic cerdip, and soic packages. also available in tape and reel in accordance with eia-481a standard general description the ad845 is a fast, precise, n channel jfet input, monolithic operational amplifier. it is fabricated using analog devices complementary bipolar (cb) process. advanced laser-wafer trimming technology enables the very low input offset voltage and offset voltage drift performance to be realized. this preci- sion, when coupled with a slew rate of 100 v/ m s, a stable unity gain bandwidth of 16 mhz, and a settling time of 350 ns to 0.01%?hile driving a parallel load of 100 pf and 500 w represents a combination of features unmatched by any fet input ic amplifier. the ad845 can easily be used to upgrade many existing designs that use bifet or fet input hybrid amplifiers and, in some cases, those which use bipolar input op amps. the ad845 is ideal for use in applications such as active filters, high speed integrators, photodiode preamps, sample-and-hold amplifiers, and log amplifiers, and for buffering a/d and d/a converters. the 250 m v max input offset voltage makes offset nulling unnecessary in many applications. the common-mode rejection r atio of 110 db over a 10 v input voltage range represents exceptional performance for a jfet input high speed op amp. this, together with a minimum open-loop g ain of 250 v/mv ensures that 12-bit perf ormance is achieved, even in unity gain buffer circuits. the ad845 conforms to the standard op amp pinout except that offset nulling is to v+. the ad845j and ad845k grade devices are available specified to operate over the commercial 0 c to 70 c temperature range. ad845a and ad845b devices are specified for operation over the ?0 c to +85 c industrial temperature range. the ad845s is specified to oper- ate over the full military temperature range of ?5 c to +125 c. both the industrial and military versions are available in 8-lead cerdip packages. the commercial version is available in an 8-lead plastic mini-dip and 16-lead soic; j and s grade chips are also available. product highlights 1. the high slew rate, fast settling time, and dc precision of the ad845 make it ideal for high speed applications requiring 12-bit accuracy. 2. the performance of circuits using the lf400, ha2520, ha2522, ha2525, ha2620, ha2622, ha2625, 3550, opa605, and lh0062 can be upgraded in most cases. 3. the ad845 is unity gain stable and internally compensated. 4. the ad845 is specified while driving 100 pf/500 w loads. plastic mini-dip (n) package and cerdip (q) package 16-lead soic (r-16) package rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved.
ad845especifications rev. e e2e (@ 25 c and 15 v dc, unless otherwise noted.) ad845j/a ad845k/b ad845s parameter conditions min typ max min typ max min typ max unit input offset voltage 1 initial offset 0.7 1.5 0.1 0.25 0.25 1.0 mv t min to t max 2.5 0.4 2.0 mv offset drift 20 1.5 5.0 10 m v/ r c input bias current 2 initial v cm = 0 v 0.75 2 0.5 1 0.75 2 na t min to t max 45/75 18/38 500 na input offset current initial v cm = 0 v 25 300 15 100 25 300 pa t min to t max 3/6.5 1.2/2.6 20 na input characteristics input resistance 10 11 10 11 10 11 k w input capacitance 4.0 4.0 4.0 pf input voltage range differential 20 20 20 v common-mode 10 +10.5/e13 10 +10.5/e13 10 +10.5/e13 v common-mode rejection v cm = 10 v 86 110 94 113 86 110 db input voltage noise 0.1 hz to 10 hz 4 4 4 m v p-p f = 10 hz 80 80 80 nv/ hz hz hz hz hz hz hz hz hz hz hz h hz hz hz h hz
ad845 rev. e ? ordering guide temperature package package model range description option 1 ad845jn 0 c to 70 c 8-lead pdip n-8 ad845kn 0 c to 70 c 8-lead pdip n-8 ad845jr-16 0 c to 70 c 16-lead soic r-16 ad845jr-16-reel 0 c to 70 ct ape and reel r-16 ad845jr-16-reel7 0 c to 70 ct ape and reel r-16 ad845aq ?0 c to +85 c 8-lead cerdip q-8 ad845bq ?0 c to +85 c 8-lead cerdip q-8 ad845sq ?5 c to +125 c 8-lead cerdip q-8 ad845sq/883b ?5 c to +125 c 8-lead cerdip q-8 5962-8964501pa 2 ?5 c to +125 c 8-lead cerdip q-8 ad845jchips 0 c to 70 cdie notes 1 n = plastic dip; q = cerdip; r = small outline ic (soic). 2 see military data sheet. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 plastic mini-dip . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.6 w cerdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.4 w 16-lead soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5 w input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +v s output short-circuit duration . . . . . . . . . . . . . . . . indefinite differential input voltage . . . . . . . . . . . . . . . . . . +v s and ? s storage temperature range q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 c to +150 c n, r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 c to +125 c lead temperature range (soldering 60 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 mini-dip package: q ja = 100 c/w; cerdip package: q ja = 110 c/w; soic package: q ja = 100 c/w. metalization photograph dimensions shown in inches and (mm). contact factory for latest dimensions. substrate connected to +v s
tpc 1. input voltage swing vs. supply voltage tpc 4. quiescent current vs. supply voltage tpc 7. input bias current vs. common-mode voltage ad845etypical performance characteristics rev. e e4e tpc 2. output voltage swing vs. supply voltage tpc 5. input bias current vs. temperature tpc 8. short-circuit current limit vs. temperature tpc 3. output voltage swing vs. resistive load tpc 6. magnitude of output impedance vs. frequency tpc 9. unity-gain bandwidth vs. temperature
ad845 rev. e e5e tpc 10. open-loop gain and phase margin vs. frequency tpc 13. common-mode rejection vs. frequency tpc 16. harmonic distortion vs. frequency tpc 11. open-loop gain vs. supply voltage tpc 14. large signal frequency response tpc 17. input noise voltage spectral density tpc 12. power supply rejection vs. frequency tpc 15. output swing and error vs. settling time tpc 18. slew rate vs. temperature
ad845 rev. e e6e tpc 19. recommended power supply bypassing tpc 22. unity gain follower tpc 25. unity gain inverter tpc 20. ad845 simplified schematic tpc 23. unity gain follower large signal pulse response tpc 26. unity gain inverter large signal pulse response tpc 21. offset null configuration tpc 24. unity gain follower small signal pulse response tpc 27. unity gain inverter small signal pulse response
ad845 rev. e e7e measuring ad845 settling time figure 1 shows ad845 settling time performance. this measure- ment was accomplished by driving the amplifier in the unity gain inverting mode with a fast pulse generator. the input sum ming junction was measured using false nulling techniques. settling time is defined as the interval of time from the application of an ideal step function input until the closed-loop amplifier output has entered and remains within a specified error band. components of settling time include: 1. propagation time through the amplifier 2. slewing time to approach the final output value 3. recovery time from overload associated with the slewing 4. linear settling to within a specified error band these individual components can be seen easily in figure 1. settling time is extremely important in high speed applications where the current output of a dac must be converted to a voltage. when driving a 500 w load in parallel with a 100 pf capacitor, the ad845 settles to 0.1% in 250 ns and to 0.01% in 310 ns. figure 1. settling characteristics 0 v to 10 v step upper trace: output of ad845 under test (5 v/div) lower trace: error voltage (1 mv/div) figure 2. settling time test circuit a high speed instrumentation amp the 3-op amp instrumentation amplifier circuit shown in figure 3 can provide a range of gains from unity up to 1000 and higher. the instrumentation amplifier configuration features high common-mode rejection, balanced differential inputs, and stable, accurately defined gain. low input bias currents and fast settling are achieved with the fet input ad845. most monolithic instrumentation amplifiers do not have the high frequency performance of the circuit in figure 3. the cir- cuit bandwidth is 10.9 mhz at a gain of 1 and 8.8 mhz at a gain of 10; settling time for the entire circuit is 900 ns to 0.01% for a 10 v step (gain = 10). the capacitors employed in this circuit greatly improve the amplifier?s settling time and phase margin. figure 3. high performance, high speed instrumentation amplifier table i. performance summary for the 3-op amp instrumentation amplifier circuit 3-op amp in-amp small signal settling time gain r g bandwidth to 0.01% 1o pen 10.9 mhz 500 ns 22 k w 8.8 mhz 500 ns 10 226 w 2.6 mhz 900 ns 100 20 w 290 khz 7.5 m s note: resistors around the amplifiers? input pins need to be small enough in value so that the rc time constant they form, with stray circuit capacitance, does not reduce circuit bandwidth. figure 4. the pulse response of the 3-op amp instrumentation amplifier. gain = 1, horizontal scale = 0.5 ms/div and vertical scale = 5 v/div.
ad845 rev. e e8e figure 5. settling time of the 3-op amp instrumentation amplifier. horizontal scale is 200 ns/div, vertical scale, positive pulse input is 5 v/div and output settling is 1 mv/div. figure 6. settling time of the three op amp instru- mentation amplifier. horizontal scale: 200 ns/div; vertical scale, negative pulse input: 5 v/ div; output settling: 1 mv/div. driving the analog input of an a/d converter an op amp driving the analog input of an a/d converter, such as that shown in figure 7, must be capable of maintaining a constant output voltage under dynamically changing load condi- tions. in successive approximation converters, the input current is compared to a series of switched trial currents. the compari- son point is diode clamped but may deviate several hundred millivolts, resulting in high frequency modulation of a/d input current. the output impedance of a feedback amplifier is made artificially low by the loop gain. at high frequencies, where the loop gain is low, the amplifier output impedance can approach its open-loop value. most ic amplifiers exhibit a minimum open-loop output impedance of 25 w due to current limiting re sistors. a few hundred microamps reflected from the change in converter loading can introduce errors in instantaneous input voltage. if the a/d conversion speed is not excessive and the bandwidth of the amplifier is sufficient, the amplifier?s output will return to the nominal value before the converter makes its comparison. however, many amplifiers have relatively narrow bandwidth, yielding slow recovery from output transients. the ad845 is ideally suited to drive high resolution a/d converters with 5 m s or longer conversion times since it offers both wide bandwidth and high open-loop gain. figure 7. ad845 as adc unity gain buffer
ad845 rev. e e9e outline dimensions 8-lead plastic dual in-line package [pdip] (n-8) dimensions shown in inches and (millimeters) seating plane 0.180 (4.57) max 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 8 1 4 5 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.100 (2.54) bsc 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-095aa 0.015 (0.38) min 16-lead standard small outline package [soic] wide body (r-16) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013aa seating plane 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 16 9 8 1 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 10.50 (0.4134) 10.10 (0.3976) 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) 8-lead ceramic dual in-line package [cerdip] (q-8) dimensions shown in inches and (millimeters) 1 4 85 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.055 (1.40) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.405 (10.29) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) controlling dimensions are in inches; millimeters dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design
ad845 rev. e e10e revision history location page 10/03?data sheet changed from rev. d to rev. e. renumbered figures and tpcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
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